Modeling Time-triggered Architecture Based Safety-critical Embedded Systems Using Systemc ........ 10 5bcmffpgg$poufout 5bcmffpgg$poufout 5bcmffpgg$poufout 5bcmffpgg$poufoutt Mixed Signal Simulation with Systemc and Saber

Increasing complexity and heterogeneity leads to systems that combine the aspects of both digital hardware/software and mixed-signal embedded systems. A major difficulty is the fact that the components for mixed-signal systems are designed bottom-up, while a digital hardware/software system is designed topdown. Often this requires co-simulation, in practice involving multiple simulators from different vendors and on different platforms. Unfortunately, setting up cosimulations is a timeconsuming task which is therefore done only a few times for verification purposes. In this paper we show how a plain SystemC simulation can be connected to Saber. A proxy module interfaces to the SystemC simulation and relays signals to Saber. A special signal synchronisation and update scheme ensures the availability of current analogue values to SystemC starting from the very beginning of each time step. Furthermore we introduce a mechanism for automatically connecting SystemC modules and show how it can be used to implement a graphical SystemC editor. A design example which compares a SystemC to Saber cosimulation to a functionally identical SystemC-AMS simulation is also included.